Nobody Hammer

I break chips on purpose: side-channel analysis, fault injection and IoT security, plus the full-stack tools that make the lab work faster.

Fig. 1: CPA on AES-128, key byte 0Traces: 1 · k[0] = -- · in progress

An EM probe listens while the chip encrypts. Wrong key guesses stay flat; the right one spikes where the S-box output leaks.

Selected work

§ 2 · 2 entries

BetaCortex-MFull-stack
SimuSCA
A side-channel leakage simulator for Cortex-M. It runs real firmware and produces power traces, so attacks and countermeasures can be tested without a lab bench.
Read the project page →Request a demo →
1. Mark the code under test with two breakpoints; the firmware is rebuilt to match.
2. Run live, labelled campaigns on ready examples: AES-128 and RSA.
3. Click a leakage peak and jump to the instruction that caused it.
4. Check countermeasures: square-and-multiply leaks its key through timing, the Montgomery ladder doesn't.
Debug Probe
A custom SWD/JTAG probe, from the board to the firmware, for working on evaluation hardware.
In development